What are the rules for good RF PCB layout?
Good RF PCB layout rests on an unbroken ground plane directly under RF traces, controlled-impedance lines of known stackup, short and direct RF paths, generous ground via stitching, physical separation and shielding between high-gain or high-power stages, and careful supply decoupling. The return current of a high-frequency signal flows in the plane directly beneath its trace, so plane splits under RF lines create loops that radiate and couple.[1][2]
What are the core layout rules?
- Use a solid ground layer immediately below the RF layer; avoid routing other signals in it.
- Route RF traces at the calculated width, with smooth bends (mitered or curved) and no stubs.
- Place matching components close to the device pins; follow reference layouts for RF ICs.
- Keep LNA inputs away from PA outputs, VCOs and digital clocks.
- Stitch ground pours with vias spaced well under λ/10 (λ/20 is common at the highest frequency of concern).
- Put multiple vias at every ground pad of RF components to lower inductance.
How should transitions be handled?
Connector launches, layer changes and IC pads are discontinuities. Model them with EM simulation, use ground return vias next to signal vias, back-drill or minimize via stubs at high frequencies, and match pad sizes to line widths where possible.
How are digital and RF mixed on one board?
Partition the board into regions without splitting the ground plane under RF; route digital lines away from RF; filter supplies entering RF regions; use shields over sensitive sections; and control clock harmonics that may fall in receive bands.[1]
How do you verify layout?
EM-simulate critical structures, check impedance on fabricated coupons with TDR, measure S-parameters, and use near-field probes to locate radiating hot spots.
Frequently asked questions
Should I split ground planes?
Generally no under RF; partition by placement and keep one continuous reference.
How close should ground vias be?
Commonly λ/20 or less at the highest frequency of concern.
Do 90° bends matter?
Below a few GHz a little; mitering reduces the excess capacitance.
See also
References
Online sources accessed October 21, 2026; printed works cited by edition. See all sources.
- “Electromagnetic Compatibility Engineering”. H. W. Ott, Wiley. 2009.
- “High-Speed Layout Guidelines (SCAA082) and RF layout application reports”. Texas Instruments. application report.