How does direct digital synthesis (DDS) work?
A DDS uses an N-bit phase accumulator incremented by a frequency tuning word (FTW) each clock cycle, a phase-to-amplitude converter (sine lookup), and a DAC. The output frequency is fout = FTW·fclk/2N, with resolution fclk/2N; a 32-bit accumulator at 1 GHz gives about 0.23 Hz steps. DDS offers fast, phase-continuous switching but is limited by Nyquist and DAC spurs.[1]
What limits DDS output?
- Maximum useful output is below fclk/2; practical designs use up to about 40% of fclk to leave room for the reconstruction filter.
- DAC zero-order hold imposes a sinc(f/fclk) amplitude rolloff (−3.9 dB at Nyquist).
- Images at k·fclk ± fout must be filtered.
Where do DDS spurs come from?
Phase truncation (using fewer bits than the accumulator to address the lookup), amplitude quantization, and DAC nonlinearity. Phase dithering and careful FTW choice reduce truncation spurs; DAC SFDR often dominates.
How is DDS combined with PLLs?
A DDS can serve as a finely tunable reference for a PLL (the PLL multiplies DDS spurs and noise by N) or be mixed with a PLL output. Such hybrids give fine resolution and fast switching at microwave frequencies.[3]
Frequently asked questions
What is a frequency tuning word?
The phase increment added each clock, setting output frequency.
Can DDS do frequency modulation?
Yes, by changing the FTW in real time; phase and amplitude modulation are also easy.
Why filter DDS output?
To remove images and clock components.
See also
References
Online sources accessed October 21, 2026; printed works cited by edition. See all sources.
- “Wireless and RF Design / RF Source Book (collected application notes)”. Analog Devices. various.
- “The Data Conversion Handbook”. W. Kester (ed.), Analog Devices / Newnes. 2005.
- “Frequency Synthesis by Phase Lock, 2nd ed.”. W. F. Egan, Wiley. 2000.