How does fractional-N frequency synthesis work?

From RF Design Wiki · By the RF Design Wiki editorial team · Published October 21, 2026 · Last reviewed October 21, 2026 · How we research

A fractional-N synthesizer alternates the feedback divider between integer values so that the average division ratio is N + F/M. This allows a high PFD frequency (lower in-band noise, wider loop bandwidth) with fine frequency steps. A delta-sigma modulator controls the division sequence and pushes the resulting quantization noise to high offsets where the loop filter suppresses it.^[1]^[2]

Why does fractional-N improve phase noise?

For a given step size, an integer-N PLL needs f_PFD equal to the step; fractional-N can use a far higher f_PFD, reducing N. Since in-band noise rises as 20·log10(N) and falls with 10·log10(f_PFD) for a fixed normalized floor, the net improvement is about 10·log10 of the ratio of PFD frequencies.^[2]

What are fractional spurs?

Periodic divider patterns create spurs at offsets related to the fractional frequency. Higher-order delta-sigma modulators with dither randomize the pattern; charge-pump linearity is critical because nonlinearity folds shaped high-frequency noise back in-band. Integer-boundary spurs occur when the output is close to an integer multiple of f_PFD, and are avoided by frequency planning.^[2]

What did Riley et al. contribute?

Their 1993 paper established delta-sigma modulation for controlling the fractional divider, replacing older accumulator-based compensation schemes.^[1]

Frequently asked questions

What resolution can fractional-N achieve?

Sub-hertz with long modulator word lengths.

Is fractional-N noisier?

Shaped quantization noise rises at high offsets; with proper loop filtering performance is usually better overall.

What is MASH?

A multi-stage noise-shaping delta-sigma modulator architecture common in synthesizers.

References

Online sources accessed October 21, 2026; printed works cited by edition. See all sources.

“Delta-Sigma Modulation in Fractional-N Frequency Synthesis”. T. A. D. Riley, M. A. Copeland, T. A. Kwasniewski, IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559. May 1993.
“PLL Performance, Simulation, and Design”. D. Banerjee, Texas Instruments. 5th ed., 2017.

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