How do you design a PCB stackup for controlled impedance?
A controlled-impedance stackup fixes dielectric thicknesses, materials and copper weights so that traces of specified width meet a target impedance, typically 50 Ω single-ended and 90–100 Ω differential. Designers specify target impedances and reference layers, calculate widths with a field solver, and fabricators adjust within tolerance (commonly ±10%) and verify with test coupons.[1]
How should layers be assigned?
- Layer 1: RF components and microstrip/GCPW.
- Layer 2: solid ground reference, as thin a dielectric above as practical to reduce line width sensitivity and via inductance.
- Inner layers: power, digital routing, stripline.
- Keep stackup symmetric to avoid warp.
What affects the impedance?
Dielectric thickness and Dk dominate; trace width (including etch trapezoid), copper thickness, solder mask and plating also matter. A thin RF dielectric (e.g., 0.1–0.25 mm) gives narrow 50 Ω lines compatible with small IC pads.[1]
How is impedance verified?
Fabricators measure coupons with TDR; designers can request coupon reports. For RF-critical designs, also measure insertion loss and phase on test lines. See TDR.
Frequently asked questions
Should RF traces be on the outer layer?
Usually, for direct component access; stripline is used for isolation.
What tolerance is typical?
±10% is a common standard; tighter tolerances cost more.
Do I need the fabricator's input?
Yes; their materials and processes determine achievable widths and thicknesses.
See also
References
Online sources accessed October 21, 2026; printed works cited by edition. See all sources.
- “IPC-2141A: Design Guide for High-Speed Controlled Impedance Circuit Boards”. IPC. 2004.