How does a phase-locked loop work?
A phase-locked loop (PLL) frequency synthesizer locks a VCO to a stable reference. A phase-frequency detector (PFD) compares the reference (divided by R) with the VCO output divided by N; a charge pump and loop filter convert the error into a VCO tuning voltage. In lock, fout = N·fref/R, so changing N steps the output in increments of fPFD = fref/R for an integer-N PLL.[1][2][3]
What are the PLL building blocks?
- Reference: crystal oscillator, TCXO or OCXO.
- PFD: tri-state detector giving both phase and frequency detection, so the loop acquires lock from any initial frequency.
- Charge pump: sources or sinks current ICP proportional to phase error duration.
- Loop filter: integrates current into voltage and sets dynamics (see loop filter design).
- VCO with gain KVCO.
- Feedback divider N (prescaler plus counters, or fractional-N).
How does phase noise behave in a PLL?
Inside the loop bandwidth, output noise follows the reference and PFD/charge-pump noise multiplied by N (raised by 20·log10 N). Outside, it follows the free-running VCO. The optimum loop bandwidth is near where the two contributions cross. PLL chips specify a normalized in-band noise floor, ℒnorm (dBc/Hz), so that ℒin-band ≈ ℒnorm + 10·log10(fPFD) + 20·log10(N).[2]
What limits integer-N synthesizers?
Frequency resolution equals fPFD, so fine steps require a low fPFD, which forces large N (more in-band noise) and narrow loop bandwidth (slower settling, less VCO noise suppression). Fractional-N synthesis removes this constraint. Reference spurs appear at offsets of fPFD.[2]
Frequently asked questions
What is the PLL loop bandwidth?
The offset frequency where open-loop gain falls to unity; it sets settling time and noise shaping.
Why use a PFD rather than a mixer phase detector?
A PFD also detects frequency error and has a wide linear range, allowing reliable acquisition.
What are reference spurs?
Spurious tones at multiples of the PFD frequency caused by charge-pump leakage and mismatch.
See also
References
Online sources accessed October 21, 2026; printed works cited by edition. See all sources.
- “Phase-Locked Loops: Design, Simulation, and Applications, 6th ed.”. R. E. Best, McGraw-Hill. 2007.
- “PLL Performance, Simulation, and Design”. D. Banerjee, Texas Instruments. 5th ed., 2017.
- “MT-086: Fundamentals of Phase Locked Loops (PLLs)”. Analog Devices. tutorial.
- “Charge-Pump Phase-Lock Loops”. F. M. Gardner, IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858. November 1980.