How do you design a PLL loop filter?

A charge-pump PLL with a passive loop filter is designed by choosing a loop bandwidth ω_c and phase margin (commonly 45°–60°) and computing component values. The open-loop gain is G(s)H(s) = ICP·Z(s)·KVCO/(N·s) with K_VCO in rad/s/V; the filter Z(s) must include a zero to stabilize the type-2 loop.^[1][2]

What is the standard topology?

The common passive second-order filter is C₁ in parallel with a series R₂–C₂. R₂C₂ forms the zero (below ω_c) and C₁ adds a pole above ω_c to suppress charge-pump ripple. A third-order filter adds an R₃–C₃ section for extra reference-spur attenuation.^[1]

How do you choose loop bandwidth?

• Wide bandwidth: fast settling and more VCO noise suppression, but less reference spur filtering.
• Narrow bandwidth: cleaner spurs and reference noise, slower lock.
• Keep ω_c well below the PFD frequency; Gardner showed sampled-loop instability as bandwidth approaches a fraction of the comparison frequency, and a common practice is f_c ≤ f_PFD/10.^[2]

What about K_VCO variation?

K_VCO often varies by 2× or more across the tuning range, and N changes across channels, so loop bandwidth and phase margin shift. Designs are checked at extremes; some synthesizers scale I_CP to compensate. Simulation tools from PLL vendors calculate component values and phase noise.^[3][1]

Frequently asked questions

See also

• PLL basics
• Fractional-N synthesis
• VCO design
• Phase noise

References

Online sources accessed October 21, 2026; printed works cited by edition. See all sources.

1. “PLL Performance, Simulation, and Design”. D. Banerjee, Texas Instruments. 5th ed., 2017.
2. “Charge-Pump Phase-Lock Loops”. F. M. Gardner, IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858. November 1980.
3. “PLLatinum Sim / PLL design documentation and application reports”. Texas Instruments. various.