How do you convert phase noise to jitter?
RMS jitter is obtained by integrating phase noise over an offset range: σt = √(2·∫ 10ℒ(f)/10 df) / (2πf0), where the factor 2 accounts for both sidebands. The integration limits (e.g., 12 kHz to 20 MHz for many communications clocks) must always be stated.[1]
What is a worked example?
Suppose a 100 MHz clock has a flat ℒ(f) = −150 dBc/Hz from 10 kHz to 20 MHz. Integrated single-sideband power = −150 + 10·log10(2×107) ≈ −77 dBc. Double it (+3 dB) to −74 dBc → phase variance 4.0×10−8 rad², σφ = 0.20 mrad. σt = 0.20×10−3/(2π·108) ≈ 0.32 ps rms.
How does jitter limit ADC SNR?
For a full-scale sine at fin sampled with rms aperture jitter σt, SNR = −20·log10(2πfinσt). At 1 GHz input and 100 fs jitter, the limit is 64 dB, independent of resolution. This is why direct-RF sampling converters need very clean clocks.[1][2]
What jitter definitions exist?
Period jitter, cycle-to-cycle jitter, time interval error (TIE) and phase jitter (integrated phase noise). RF and data-converter work uses integrated phase jitter; digital timing work often uses period and cycle-to-cycle jitter with peak values estimated from rms for a target bit error rate.
Frequently asked questions
Why integrate from 12 kHz to 20 MHz?
It is a common range in telecom clock specifications; always state the range used.
Does dividing a clock reduce jitter?
Absolute time jitter is not reduced, but phase noise in dBc/Hz falls by 20·log10(N).
What jitter does an ADC need?
It depends on input frequency and target SNR, per the SNR formula.
See also
References
Online sources accessed October 21, 2026; printed works cited by edition. See all sources.
- “MT-008: Converting Oscillator Phase Noise to Time Jitter”. W. Kester, Analog Devices. tutorial.
- “The Data Conversion Handbook”. W. Kester (ed.), Analog Devices / Newnes. 2005.